There are several reconfigurable network models of parallel computation that are considered in the published literature depending on their switching capabilities, given an algorithm which is designed for a large reconfigurable mesh. Can it be executed the two algorithms of binary addition of two numbers and matrix multiplication. these can be carried out optimally on smaller reconfigurable mesh and using standard methods on the mode in which buses are established along rows or columns using the unit-time delay model. Parallel computers are based on a collection of processors and switching nodes connected by a fast interconnection network traditional design are based on a fixed topology, but now the concept of reconfigurable network has come into existence. The basic idea of a reconfigurable network is to enable flexible connection patterns by allowing nodes to connect and disconnect their adjacent edges in various patterns. This yields a variety of possible topologies for the network and enables the program to exploit this topological variety in order to speed up the computation. Informally a reconfigurable network operates as follows. The edges of the network are viewed as building blocks for larger bus components. The network dynamically reconfigures itself at each time step. Where an allowable configuration is a partition of the network into a set of edge-disjoint buses. A crucial point is that the reconfigurable process is carried out locally at each processors of the network. i.e. at the beginning of eah step during the execution of a program.
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Cite this article:
Saxena and Chaudhari (1999). Parallel Algorithms For Addition And Multiplication For Reconfigurable Arrays. Journal of Ravishankar University (Part-B: Science), 12(1), pp.25-30.