Low Noise Amplifier Design at GHz-Frequencies: A Review of Recent Advances and Challenges

SachchidaNand Shukla^1,*, Syed Shamroz Arshad², Geetika Srivastava³, Kavita Thakur⁴

¹Pt. Ravishankar Shukla University Raipur, Chhattisgarh and

 Department of Physics and Electronics (on lien), Dr Ram Manohar Lohia Avadh University, Ayodhya, Uttar Pradesh

^2,3Department of Physics and Electronics, Dr Ram Manohar Lohia Avadh University, Ayodhya, Uttar Pradesh

⁴School of Studies in Electronics and Photonics, Pt. Ravishankar Shukla University Raipur, Chhattisgarh

Abstract

The Darlington and Sziklai transistor pairs have emerged as promising alternatives to conventional single-transistor configurations due to their advantageous combination of wide bandwidth and high gain at lower drive voltages. This review presents a detailed examination of various design approaches for developing Low Noise Amplifiers (LNAs) operating in the GHz frequency range, with particular emphasis on these transistor pair topologies. A total of 45 research sources published between 2015 and 2026 were initially surveyed, out of which 36 were found relevant to the objective of review. The analysis shows that Darlington pair–based CMOS operational amplifiers deliver the highest gain, while Sziklai pair–based NMOS and PMOS LNAs offer the broadest bandwidth compared to conventional LNA architectures. These findings strongly support the core hypothesis regarding their suitability for ultra-wideband GHz applications. The review concludes by highlighting the key challenges associated with implementing these LNAs at GHz frequencies.

Keywords: Darlington pair, Sziklai pair, Wireless communication, Low Noise Amplifiers, CMOS

Introduction

The wireless communication industry has been a profitable market for semiconductor companies in the last few years. Wireless technologies have a wide range of applications in sending and receiving data quickly in both personnel and business work. As per the recent survey, it has been found that more than 18.22 billion wireless equipment are sold worldwide in the financial year 2025 (Forecast number of mobile devices worldwide from 2020 to 2025 (in billions) *, 2025). The global electronics market for mobile communication is rapidly increasing and the communication industry is searching for the technology that can deliver advanced capabilities and higher circuit performance.

The need for mobile communications and instantaneous access to the messages, at any moment, considerably changed the customer electronics business. Exchange of the data through mobile handsets, tablets, computers and other types of portable communications are experiencing record progress. Therefore, to meet out the demand and need of market, cellular networks are working towards increasing their data rate speed. The emerging 6G technology targeting the data rates up to 1000 Gigabits-per-seconds, therefore to allow this high data-transfer speed, the bandwidth has to be increased (Liu et al. 2019)

 This boom has provided an extraordinary chance for wireless communication industry for picking the innovative semiconductor technology from substrate materials to device to design RF front-end blocks of wireless communication system. Block diagram of general wireless communication system is shown in Fig 1.

 Fig. 1. Block Diagram of Wireless Communication System (Singh et al. 2013)

The key components used in RF front-end blocks, are low noise amplifier (LNA), power amplifier (PA) and mixer. These components require low noise, high gain, high linearity, and low power consumption to produce higher circuit performances. There are various technologies available for designing LNA such as SiGe heterojunction bipolar technology (HBT), SiCMOS, high-electron-mobility-transistor (HEMT), CMOS and BiCMOS. Therefore, for wireless communication system, novel technologies need to be investigated, so that conditions for the modern wireless communication system with higher circuit performance can be realized.

In this review, study of the reported low noise amplifiers at GHz frequency and related challenges with a special reference to multi-BJT based devices has been performed for front-end-blocks of wireless communication system applications.

Methodology

Literature Search Strategy

Research papers published between 2015 to 2026 are collected from the different research and key words used to retrieved papers from these databases are: (1) Low Noise Amplifiers, (2) GHz range Low Noise Amplifiers, (3) Technologies for GHz range Low Noise Amplifier, and (4) Low Noise Amplifier topologies. Inclusion criteria for the research papers are as follows: (i) papers must be published between 2015 and 2026; (ii) papers should have at least 2 citations (iii) papers must be available in the database; (iv) papers showing improvement either in gain, bandwidth, or noise. Abstracts published in conferences, articles which have bandwidth below 1 MHz range, review papers, website materials, and thesis are excluded from this review study.

 Selection of studies and data extraction

Based on the literature search strategy, research papers relevant to inclusion criteria were scrutinized from electronic research database and those papers found under the exclusion criteria are removed from the review process. Following parameters are observed from the selected papers: (1) Bandwidth, (2) Gain, (3) Power Consumption, (4) Input P1 dB, (5) IIP3, (6) Noise Figure, (7) Chip Area, (8) Number of stages, (9) Device Type, (10) Technique.  These parameters are arranged in tabular form for different types of techniques and topologies. Fig. 2 shows the flow chart consisting of meta-analysis for this review study.

Fig.2. Meta analysis of the review study

Research Gap, Research Contribution and Research Question

Most of the research papers in the literature is filled with the review of Low Noise amplifiers (LNAs) operating at 2.4 GHz technology. However, present review, focussing on the different types of technologies and topologies, offers a comprehensive review of recently reported LNAs operating up to 580.554 GHz bandwidth and 70 dB gain along with description over emerging semiconductor topologies, future research directions and related bottlenecks for GHz range applications.   

This review provides comprehensive review of different LNA topologies operating up to 580.554 GHz bandwidth and 70 dB gain. As a novel contribution, this review study found Sziklai pair and other multi BJT based electronic pairs suitable for UWB applications due to its high gain and wide band feature. This review also provides issues and challenges for future UWB applications.

This review study is basically performed to answer the questions: What are the different technologies and techniques available to design Low Noise Amplifiers at GHz range? What are the issues and challenges for LNA operating at GHz range frequency?

Approaches to improve the Bandwidth for GHz applications

High Electron Mobility Transistor (HEMT) Process

A high electron mobility transistor (HEMTs) is a type of FET that uses two semiconductors’ materials having different band gaps in a junction (Nikandish el al. 2014). It is also known as Heterostructure FET (HFET) and modulation-doped FET (MODFET). Materials combinations of GaAs (Gallium Arsenide) and AlGaAs (Aluminium Gallium Arsenide) are generally used to constitute HEMT.

Gallium arsenide (GaAs) is good choice for GHz applications due to their high mobility, high breakdown voltage, high Q values for the passive components and better linearity. However, this semiconductor technology faces some restrictions such as poor tunability, low thermal conductivity, high RF loss, complex digital integration, high cost, high power consumption and complex fabrications.

Recently, GaN (Gallium Nitride) is widely used in HEMTs due to its high-power characteristics, whereas for high frequency applications, it is found that HEMTs with In (indium) shows better performances. These transistors are extensively used in low power RF applications, satellite receivers, and defense department.

There are two versions of HEMT are available e.g., pHEMT (Pesodomorphic HEMT), mHEMT (metamorphic HEMT). The pHEMT is achieved by using thin layer of one of the semiconductor materials which creates larger bandgap and ultimately produces better performances. However, mHEMT is an improved versions of pHEMT which uses a buffer layer between the semiconductor’s materials having different lattice constant.

(Zencir et al. 2026) recently investigated single stage GaN low noise amplifier in common source mode using RLC feedback technique at 0.25 µm GaN HEMT. At 12V supply voltage, this design generates 16 dB power gain across 20 MHz to 2 GHz bandwidth along with a noise figure less than 1.3 dB and consumes 1.9 W power.

(Moschetti et al. 2015) proposed the five stage Common source MMIC amplifier in 50nm mHEMT technology. This five-stage amplifier generates 178-185 GHz bandwidth with 24.5 dB gain, and 24 mW DC power consumption.

(Chou et al. 2016) proposed a Darlington pair power MMIC amplifier implemented in 0.5µm GaN-on-SiC HEMT technology. This configuration utilizes the cascode technique to improve the gain and bandwidth. Operating at 30V DC supply voltage, this amplifier exhibits 15 dB gain, 1.0GHz to 5.8 GHz bandwidth with 330 mW DC power consumption. This amplifier is suitable in X-band high power wireless access point.

(Thome et al. 2022) proposed two distributed down converters MMICs 35-nm InGaAs mHEMT Technology, where first MMIC1 represents mixer whereas second MMIC2 shows enhanced version of MMIC1 with the eight-cell local oscillator (LO) driver amplifier. Using this topology, the MMIC2 reports the 1-170 GHz bandwidth is achieved with -4.2 dB gain and 180mW DC power consumption.

(Yan et al. 2023) proposed a two-stage wideband low-noise amplifier MMIC (Monolithic Microwave integrated Circuit) with multiple resistive feedback in a 0.15- μm GaAs E-mode pHEMT technology which features 1.0 to 12.5 GHz bandwidth, 23.6 peak gain, 87.5 mW power consumption with a compact die size of only 0.75 mm².

(Yuan et al. 2024) proposed three-stage cascode low noise amplifier (LNA) in a 0.15- μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology. The first two stages use transformer feedback whereas the third stage employs Darlington pair. The results show that the proposed architecture achieves gain of 23.4 dB in the operating band from 0.5 GHz to 30 GHz with 246 mW power consumption and 2.2 x 0.7 mm² area.

Table 1 summerizes the parameters of these LNA in respect of frequency, gain, DC power consumption, chip area, number of stages, device type, and technology.

Table 1: Summary of the LNAs based on HEMT technology

^* Power Gain

 Heterojunction Bipolar Transistor (HBT) Process

The Heterojunction Bipolar Transistor is a type of BJT which uses dissimilar semiconductor materials for base and emitter (Zhu et al 2023). The advantages of HBT are high power density, high efficiency, and high frequency performances. There are two types of HBTs available,

·       SHBT (Single heterojunction bipolar transistor)

·       DHBT (Double heterojunction bipolar transistor)

Heterojunction transistor is generally formed when emitter is made up of wide band gap semiconductors (AlInAs or InP) and base is made up of narrow band gap semiconductors (GaInAs). In SHBT, same semiconductors are used for collector and base whereas, different semiconductors are used in the formation of DHBT.

(Kundu et al. 2026) presented the design of SiGe HBT based low noise amplifier for radio frequency front end receivers using Keysight’s Advanced Design System (ADC). This design achieves power gain (S₂₁) of 33.409 dB at 3 GHz bandwidth along with NF of 0.931 dB.  

(Eriksson et al. 2015) proposed the three Distributed amplifier topologies based on cascode gain cell in 250nm InP DHBT technology. First amplifier is a single stage Distributed amplifier which achieves 7.5 dB gain and 192 GHz bandwidth. Second amplifier is a two cascaded single stage Distributed amplifier which produces 16 dB gain and 235 GHz bandwidth. Similarly, third stage is a distributed amplifier which receives 12.8 dB gain and 180 GHz bandwidth.

(Jyo et al. 2019) reports the design of Distributed amplifier in 0.25µm Indium Phosphide (InP) DHBT technology. This amplifier uses a transmission line in cascode topology to improve the bandwidth. Under this situation, extremely wide bandwidth of 241 GHz, 10dB gain, 387 mW DC power consumption with 0.82 mm² chip area is achieved.

(Nguyen et al. 2020) proposed the nine-cell double stacked MMIC based distributed amplifier in indium phosphide (InP) DHBT technology. This design is based on the 3D interdigital capacitor C_S. This amplifier produces 10.5 dB gain, 1-160 GHz bandwidth, and 288 mW DC power consumption.

(Zhu et al 2023) presents the application of the f_T doubler technique to improve the cut-off frequency (f_T) of InP heterojunction bipolar transistors (HBTs). A f_T doubler structure was implemented by the InGaAs/InP DHBTs technique in the Institute of Microelectronics Chinese Academy of Science (IMECAS), which uses three InP DHBTs with the same emitter area of 0.8×10μm [39]. The forward Gummel plot and output characteristic of the single DHBT and f_T -doubler were compared and analyzed. The cut-off frequency (peak f_T ) of f_T -doubler is obtained as 263 GHz by extrapolating H₂₁ , while the peak f_T of single DHBT is 165 GHz. In addition, the small-signal parameters of the f_T -doubler were extracted, resulting in a good fit. This demonstrates that the reduction of Cπ is responsible for the increase in f_T, and confirms the applicability of the f_T-doubler structure as a single unit for circuit design.

Table 2 enlists performance parameters of LNA based on HBT process.

Table 2: Summary of the LNAs based on HBT technology

*Power Gain

CMOS and BiCMOS Processes

(Yadav et al. 2026) proposed the design of 28 GHz receiver front end using 3-stage differential ended LNA at 130nm BiCMOS technology. The design includes inductively degenerate cascode LNA in first stage, down mixer with common base technique in second stage, and Gm-C filter in third stage. With a gain of 30 dB and NF of 2.2 dB, this design consumes 20.9 mW power at a supply voltage of 3.3V and covers an area of 0.64 mm².

(Pandey et al. 2015) reported the design of Darlington pair CMOS Op-Amp using slew rate enhancement technique in standard 45nm CMOS Process. Under this technique, high gain of 70 dB, 1.74 GHz bandwidth, and 0.76 mW DC power consumption at ±1V supply voltage is achieved.

(Fritsche et al. 2015) proposed cascaded identical travelling wave stages based Distributed amplifier in 0.13µm SiGe BiCMOS technology. Measurement of the amplifier shows 18.7 dB gain, 180 GHz bandwidth, 86 mW DC power consumption, and 0.61 mm² chip area.  

(Singh et al. 2016) introduce the design of three Stage Darlington pair amplifier connected with positive and negative slew rate booster technique in GPDK 180nm CMOS process. Observation indicates that the slew rate of the proposed design is doubled in comparison to the conventional Darlington pair without slew rate booster technique. Using slew rate booster technique, 30 dB gain with 1.9-26.7 GHz bandwidth, and 28.4 V/µs slew rate is achieved.               

(Hasan et al. 2020) proposed the three stage CMOS power amplifier with reverse bias and power divider technique in 0.18µm CMOS silterra process. The simulation outcomes report 62.56 mW DC power consumption from 1.9V supply voltage, 8.08 dB gain, and 28 GHz bandwidth. The proposed configuration is suitable for mm-wave application and future 5G communication.

The LNA parameters based on CMOS and BiCMOS technology is recorded in Table 3.   

Table 3: Summary of the LNAs based on CMOS and BiCMOS technology

Different Techniques used to improve the Performance of LNA

Inductively Degeneration Technique

This technique is widely used in designing LNA because it provides excellent input matching, low noise figure and high gain on the cost of narrow bandwidth (Malathi et al. 2019).

To achieve input impedance matching, inductors L_g and L_s are placed at the gate and source of transistor M₁ respectively. However, inductor L_d is used for output impedance matching. The capacitor C_ext added between the gate and source of M₁ is used to control the Q value of the transistors. The output signal is received at the drain of M₂ while the input signal is applied at the gate of M₁.

(Malathi et al. 2019) reported the designs of radio frequency common gate CMOS LNA and inductively degenerated common source LNA for space exploration. The LNA was simulated with the help of HSPICE circuit simulation software at 90nm CMOS technology. Observations are made at 2GHz for both LNAs and it is found that inductively degenerate CS LNA shows better results with 31.97 dB gain, 1.04 mW power consumption, and 0.063 dB noise figure than RF CMOS CG LNA having 13.63 dB gain, 0.904 mW power consumption and 0.78 dB noise figure.

(Bansal et al. 2019) proposed the cascode CS LNA based on inductively degenerate technique. Authors have used different types of output circuit structures to observe the behavior. When R is used as load; 16.65 dB gain, 2.95 mW power consumption, and 7.802 dB noise figure is received, when L is used as load; 13.91 dB gain, 2.51 mW power consumption, and 8.419 dB noise figure is received, when LC is used as load; 26.52 dB gain, 5.011 mW power consumption, and 7.464 dB noise figure is found, and when RLC is used as load, 15.84 dB gain, 1.98 mW power consumption, and 7.784 dB noise figure is observed.   

(Prasad et al. 2022) presented the design and implementation of cascade CS LNA using 65nm CMOS technology. At supply voltage of 1 volt, 25 dB gain, less than 2.6 dB noise figure, and 2.4 GHz bandwidth are observed. 

Table 4 records the different performance metrics of LNA based inductively degenerate technique.

Table 4: Summary of the LNAs based on Inductively Degenerate technique

 Current Reuse Technique

Current reuse technique is primarily used for improving the gain of LNA (Chunhua et al. 2011). In current reuse technique, the driver transistor amplifies the input signal and current generated is used by the driver transistor which eventually lower the power consumption and noise figure while providing high gain.

(Zhang et al. 2026) reported four stage common emitter W-band current reuse low noise amplifier at 130nm SiGe process. Use of noise measure (NM) technique and source degeneration inductor alongwith metal line-based input network enabled them to achieve 20.4 dB gain, NF of 4 dB, power consumption of 12.5 mW from a supply voltage of 2.5 V across 78-106 GHz bandwidth.

Two Stage CS-CS LNA is proposed by (Shankar et al. 2015) to improve the gain using current reuse technique. Using 0.18µm CMOS technology and operating at 1.2-volt, 12.554 dB of gain, 2.874 mW of power consumption, and 5.4 GHz of wide bandwidth is received.    

(Sunganthi et al. 2022) introduced the inductor less pre-distortion two stage LNA circuit using current reuse technique at 90nm CMOS technology. The proposed LNA has three separate blocks- pre distortion circuit, current reuse blocks, and source follower circuit. Under this arrangement, 2.2 dB of gain, 7.01 mW of power consumption, 2,67 dB of noise figure, 3 dBm of P1dB, -1dBm of IIP3, and 2.4 GHz of wide bandwidth is observed.

Single stage current reuse complementary CMOS LNA is proposed by (Chang et al. 2022) for sub-6 GHz 5G system. Using body floating and self forward bias technique, this LNA occupies small area of 0.34 mm² along with 8.1±1.5 dB gain, 7.3 mW power consumption, 3.02-5.2 dB noise figure, 0.3 to -1.3 dBm IIP3 and 3.7-11.9 GHz bandwidth. Low Power consumption of this LNA is due to low power supply feature.

Different LNA based on current reuse technique are tabulated in Table 5 with their respective performance metrics.

 Table 5: Summary of the LNAs based on Current Reuse technique

Cascode Technique

This technique is used to improve the gain of LNA (Ibrahim et al. 2020). (Ibrahim et al. 2020) proposed two stage cascode pHEMT LNA with negative feedback using Advance Design System (ADS) Tool. In this design, pHEMT FHX76LP manufactured by Eudyna Devices Inc is used to study the behavior of LNA. In addition, T-matching network is used at input and output port to realize maximum power transfer. With frequency band of 5.8 GHz, this LNA shows 0.360 dB noise figure and 20.199 dB gain.

Two Stage source degenerated cascode LNA using magnetic coupling feedback technique is proposed by (Kobal et al. 2023). The proposed LNA is simulated and fabricated using 22nm FD SOI CMOS technology which shows 23.1 dB gain, 2.1 dB noise figure, -16.5 dBm IIP3 at 28 GHz, 5.6 mW power consumption while working at 23.7-28.5 GHz technology. Layout area of the LNA is 0.9 mm². 

(Yuan et al. 2024) proposed three stage cascode LNA using transformer feedback technique and Darlington pair. The Darlington pair is used in the third stage while first two stage uses transformer feedback to attain low frequency gain. Using 0.15µm GaAs pHEMT technology, this LNA consumes 246 mW power, and achieves 23.4 dB gain, 2.1 dB noise figure while operating in 0.5-30 GHz frequency band. This LNA also covers an area of 1.54 mm².

Cascode Feedback technique based LNA are tabulated in Table 6 with their respective performance metrics.

 Table 6: Summary of the LNAs based on Cascode technique

Gm boosting Technique

This technique is particularly used to enhance the transconductance (gm) of transistors (Majeed et al. 2022). Enhancing Gm leads to higher gain, wider bandwidth and low noise figure of broadband LNA.

An auxiliary transistor is inserted between gate and source terminals of transistor which provides negative voltage gain to the gate. However, this technique, due to the addition of auxiliary amplifier, enhances DC power consumption and noise figure.  

To reduce the noise figure and power consumption of common gate LNA, (Rafati et al. 2019) reported two stage UWB LNA design using noise cancellation and gm boosting topology. This design uses CG main amplifier and CS booster amplifier in first stage of gm boosting while the second stage utilize two CS amplifier and cascode CG amplifier for cancelling noise at TSMC 90 nm RF CMOS technology. The layout of LNA covers 0.67 mm² area, 14.5 dB gain, 2.2 dB noise figure in 3-5 GHz bandwidth.

(Majeed et al. 2022) proposed active inductor (AI) based three stage ultra-wide band common gate LNA using Gm boosted current reuse technique. First stage incorporates CG amplifier, second stage consists of gm boosting stage while third stage utilizes active inductor stage in the topology of the proposed LNA. Using 90nm CMOS technology, proposed LNA dissipates 10.4 mW of power, 18.0±0.8 of gain, 3.36-4.68 of noise figure, -22.8 dBm of IIP3 in the frequency range of 3.1-10.6 GHz.

Table 7 shows the Gm boosting technique based LNA in regards to frequency, gain, DC power consumption, noise figure, IIP3, area, number of stages, device type, and technology.

Table 7: Summary of the LNAs based on Gm boosting technique

Gain Inductor Peaking Technique

Gain inductor peaking technique is used to enhance the gain at high frequency and provide gain flatness in UWB LNA.

(Kazemi et al. 2021) analyzed the three-stage complementary structure based UWB LNA using series inductor peaking technique. Two complementary structure is used at first and third stage and common source amplifier is used in the second stage. Die area of 0.59 mm², power dissipation of 6.8 mW, NF of 2.2 dB, IIP3 of -4 dBm, gain of 16.05±0.45, and bandwidth of 3.1-10.6 GHz is received using 180nm CMOS technology.

Fabricated and simulated in 55nm CMOS technology, (Dong et al. 2023) proposed two stage LNA design based on resistive feedback, inductive source degeneration and coupled inductive peaking technique. With an area of 0.39 mm², this LNA receives 20.3 dB gain, 2.5 dB noise figure, 0.4-30 GHz bandwidth, and dissipated 23.5 mW of power from 1.5 V supply.

(Kim et al. 2023) proposed the design of cascode LNA using resistive feedback and inductive peaking technique at 90nm RF SOI technology. The designed LNA generates gain of 20.68 dB and 19.94 dB along with noise figure of 1.57-1.73 dB and IIP3 of -15.4 dBm. The layout area of the proposed design is 0.7 mm².  

Performance metrics of Gain inductor peaking technique based LNA is recorded in Table 8.

 Table 8: Summary of the LNAs based on Gate Inductive Peaking technique

* Power Gain

Multi transistors-based Technique: Darlington pair and Sziklai pair

The Sziklai pair topology has emerged as a promising solution for designing high-performance small-signal and low-noise amplifiers, outperforming the Darlington pair in key metrics such as gain, bandwidth, and noise figure.

Compound Sziklai pair, comprising of NMOS Sziklai pair and MOSFET based complementary Sziklai pair, were used to design low power LNA (Arshad et al. 2026). In this design, cascode feedback technique in conjunction with ITC (impedance tuning circuit) for tuning purpose were used, resulting in voltage gain of 19.51 dB with a bandwidth of 36.42 GHz and peak current gain of 39.87 dB, NF of 0.343 dB at 10 GHz, input third-order intercept point (IIP3) of 1.5 dBm, and chip area of 267.96 µm² for Ultra-Wideband (UWB) and lower millimeter-wave (mmWave) applications in RF front-end systems.

(Arshad et al. 2025) proposed NMOS and PMOS Sziklai pair amplifiers using bandwidth boosting technique at 180nm CMOS technology. The simulation results display that NMOS LNA has a bandwidth of 580.554 GHz, NF of 1.66 dB at 63.09 GHz, input P1dB of 0.883 dBm, and IIP3 of 10.22 dBm while PMOS LNA has bandwidth of 299.956 GHz, and NF of 11.71 dB at 283.09 GHz, input P1dB of 0.822 dBm, and IIP3 of 6.72 dBm. Three stage broadband distributed amplifiers (DAs) and D-band microwave tuneable second order band reject filter (BRF) are also configured by the authors using the proposed amplifiers to validate the design.

(Shukla et al. 2023) designed Complementary Sziklai pair LNA using BJTs at 180nm CMOS technology. Similar to the Sziklai pair, this innovative pair is reported to carry two opposite polarity BJTs with collector of PNP transistor is connected to the base of NPN transistor. This pair is exhaustively discussed in Chapter 5. Under CC mode, the proposed LNA generates 0.99 current gain, 0.13 voltage gain, 1.90 MHz bandwidth, 1.76E-6% THD while under CE mode, voltage gain of 200.05, current gain of 11.62, bandwidth of 1.64 MHz, and THD of 1.29E-6% is obtained.

(Nguyen et al. 2023) presented the design of Darlington cell to improve the GBP (gain bandwidth product) and output power of distributed amplifiers. Conventional Darlington pair is modified using two diode transistors to balance the voltage and current. Observations indicate that this DA produce gain of 13 dB over 3 to 230-GHz bandwidth  

Darlington pair based LNA proposed by different researchers have already been discussed earlier in (Nikandish et al. 2014, Moschetti et al. 2015, Chou et al. 2016, Pandey et al. 2015, and Mehra et al. 2017). Therefore, descriptions of these work will not be discussed here.  

Table 9 depicts performance metrics of LNA related to Sziklai pair technique.

Table 9: Summary of the LNAs based on Sziklai pair technique

Results & Discussions

The comparative discussion of all the topologies deliberated above are summarized the Table 10 based on their advantages and disadvantages.

Table 10: Comparative advantages and disadvantages of different LNA topologies

Refer Table 10. The selection of an LNA configuration technique depends on the specific application requirements. Each technique offers distinct advantages and disadvantages, which must be carefully considered.

The ‘Inductively Degenerate’ technique provides excellent input matching but not suitable for wide band applications (Malathi et al. 2019). Similarly, ‘Current Reuse’ technique improves gain while maintain minimum power dissipation but results in high input and output impedance On the other hand, ‘Cascode Technique’ provides larger band signals but occupies too much space (Ibrahim et al. 2020). Moreover, ‘Gm boosting Technique’ enhances transconductance which increases the gain but leads to high power dissipation and noise figure (Majeed et al. 2022). Inductor utilized in ‘Gain peaking inductor’ technique enhance the gain but acquires large area on chip. ‘Multi transistors-based Technique’ provides high power gain and wide bandwidth but have a limited voltage gain (Arshad et al. 2025 and Arshad et al. 2026).

Fig.3 and Fig.4 shows the bar graph of high gain and wide band LNA reported in this study respectively. The Darlington pair-based CMOS Op-Amp using slew rate enhancement technique at 45nm CMOS (Pandey et al. 2015) appears with highest bandwidth while NMOS and PMOS Sziklai LNA at CMOS 180nm (Arshad et al. 2025) technology evolves with widest bandwidth and suitable for ultra-wide band GHz application.

Fig. 3. High-Gain topologies 

Fig. 4. Wideband topologies

Challenges in Low Noise Amplifiers at GHz range frequency

At higher frequencies (above 1 GHz range), noise performance of LNA is measured in terms of noise power rather than noise voltage or noise current. It is defined as the amount of voltage measured at the output even without the input (Shukla et al. 2024). Schottky noise dominates in high performance LNA at higher frequencies which is caused by the fluctuation of current flow in semiconductors through PN junction. In Schottky noise, Mean square value of the current is expressed by equation (1),

Where q denotes electron charge, I shows forward junction current and  represents frequency bandwidth.

In addition, it is also indorsed that the supply voltage should be 2Volt or less for better performance of high frequency LNA. This is controlled by the following equation,

Where is the stage delay time, V_T and V_CC represents theshold voltage and supply voltage respectively.

Conclusion

This review reports the recent advancement in Ultra-wide band LNAs based on the different techniques and technologies. Research articles from electronic research database are collected from 2015 to 2026 year, and found that Darlington pair CMOS Op-Amp based on slew rate enhancement technique at 45nm CMOS technology (Pandey et al. 2015) appears with highest bandwidth while NMOS and PMOS Sziklai LNA at 180nm CMOS technology (Arshad et al. 2025) evolves with widest bandwidth and suitable for ultra-wide band GHz application. Different types of topologies for designing UWB LNA are also discussed which indicates that Sziklai pair topology has a high gain and wide bandwidth compared to the conventional LNA topologies and thus can be used to develop LNA for GHz range in near future.

Declarations

Conflict of Interest: The authors declare no Conflict of interests.

Funding source: This research received no external funding.

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