Sziklai Pair based Small Signal Amplifier with BJT-MOSFET Hybrid Unit at 180nm Technology

SachchidaNand Shukla¹, Syed Shamroz Arshad², Kavita Thakur³, Geetika Srivastava²

¹Pt. Ravishankar Shukla University, Raipur, Chhattisgarh and Department of Physics and Electronics (on lien), Dr. Ram Manohar Lohia Avadh University, Ayodhya, UP, India

²Department of Physics and Electronics, Dr. Ram Manohar Lohia Avadh University, Ayodhya, UP

³School of Studies in Electronics, Pt. Ravishankar Shukla University, Raipur, Chhattisgarh

Sachida.shukla@gmail.com

Abstract

Two circuit models of Small Signal amplifier, constituted with BJT-MOSFET hybrid unit under Sziklai pair topology are designed and analyzed using ‘PSpice’ and ‘Cadence Virtuoso and Spectre simulation tool (at GPDK 180nm technology)’ respectively. First amplifier (Circuit-1) uses PSpice user-defined model of BJT and MOSFET whereas the second amplifier (Circuit-2) consists of transistors available at GPDK 180nm technology. Circuit-1 can amplify the AC signals of 1mV-1nV range with optimum voltage gain 389.532, 137.570 current gain, 14.464MHz bandwidth and 2.43% THD. However, Circuit-2 can amplify AC signals of 0.1mV-10nV range with 164.018 voltage gain, 32.775 current gain, 11.906 MHz bandwidth, and 13.608E-6% THD. Both the proposed amplifier circuits remove narrow band problem and generate better results than earlier announced small signal Sziklai pair amplifier with BJT-MOSFET hybrid unit in respect of voltage and current gains, bandwidth, THD, and power consumption. Proposed amplifiers successfully address the problem of poor frequency response of small signal Darlington pair amplifier in higher frequency range and narrow bandwidth limitations of small-signal PNP Sziklai pair amplifier. Dependency of the proposed amplifiers at various biasing resistances and performance with temperature variation, noise variation, DC supply variation, and phase variation are also discussed herein. Proposed Circuits display strong dependency over ideal maximum forward beta ‘β’ of NPN transistor, Transconductance ‘V_TO’ of P-MOS transistor and additional biasing resistances ‘R_A’. Layout of Circuit-2 is found to cover 96.3898µm² area with 11.32µm length and 8.515µm breadth. Minor percentage variation between pre-layout and post-layout simulation results of Circuit-2 validates the proposed design at GPDK 180nm technology. Monte Carlo and Process Corner analysis are also performed to test the robustness and insensitivity of Circuit-2 against mean value of the parameters and process and mismatch variations respectively. Performance summary of the proposed circuits and comparison with the recently reported designs shows effectiveness of the proposed circuits in terms of power gain, THD, voltage gain, current gain, input referred noise and power gain. Qualitative analysis of the proposed Circuits recommends its usability as Low Noise Amplifier in the portable RF noise measurement system.

Key Words: Sziklai pair, Small signal amplifier, compound pair   

Introduction

For a variety of electronics and communication system applications, the preferred device configurations are the Darlington and Sziklai Pairs [1]-[4]. Due to the identical ranges for input impedance, output impedance, voltage gain, and current gain factor ‘β’, Darlington and Sziklai pairs are regarded as complementary to one another in many applications [4]-[5]. But now-a-days, Sziklai pair gradually replacing the Darlington pair in small-signal amplifiers, power amplifiers and digital circuits because of its half base turn-ON voltage, low power dissipation, and better switching speed than Darlington pair [5].

In order to combine the required qualities of JFETs and BJTs, Aina et al. (1993) first ever used a JFET-BJT hybrid unit based small-signal amplifier under Darlington pair topology [6]. They concurrently obtained high input impedance and high current gain. These coordinated efforts have resulted in the usage of a number of devices in hybrid combinations under Darlington pair and Sziklai pair topology by many researchers [6]-[13]. The BJT and MOSFET hybrid unit based Sziklai pair amplifier had been reported by Shukla et al. in 2015 which crops high voltage gain, moderate current gain with low THD [7].

This manuscript reports modified version of two small-signal amplifiers circuits with BJT-MOSFET hybrid unit under Sziklai pair topology. These circuits not only resolve the narrow band problem found in [7] and PNP Sziklai pair Small Signal Amplifier but also resolves the poor response problem of small signal Darlington pair amplifier at higher frequency [12], [14]-[15]. The key merits of the reported circuits are their high voltage and current gains, wide bandwidth, low power consumption, and low input referred noise.

Circuit Details

Circuit designs of Proposed amplifiers, as sketched in Fig.1(a) and Fig.1(b), are referred herein as Circuit-1 and Circuit-2 respectively. Circuits of Fig.1(a) and Fig.1(b) accommodate NPN type BJT at driver position and P-type MOSFET at follower position under Sziklai pair topology. Respective circuits of proposed amplifiers are analyzed with the aid of PSpice (Student Version 9.2), and Cadence Virtuoso and Spectre Simulation (at GPDK 180nm technology) tools [16]-[17]. Proposed amplifier (Circuit-1) accommodates user defined PSpice model of BJT (QMODN with β=300) at driver position and P-type MOSFET (PMOSD with V_TO=-2) at follower position under Sziklai pair topology [16].  

Fig.1(a). Proposed Amplifier (Circuit-1) under PSpice Simulation tool

Fig.1(b). Proposed Amplifier (Circuit-2) under Cadence Virtuoso and Spectre Simulation tool at GPDK 180nm technology

Qualitative performance of the proposed amplifiers is observed with 1mV, 1KHz AC input signal source. However, the Circuit-1 and Circuit-2 produce undistorted output for 1mV-1nV and 0.1mV-10nV range of AC input at 1KHz respectively.

Results And Discussions

A.    Performance Parameters

Comparative values of the performance parameters of the Proposed amplifiers (Circuit-1 and Circuit-2) with Commercial transistor based BJT-MOSFET Sziklai pair amplifier (Reference Amplifier) are listed in Table-3. Circuit-1 describes the PSpice user-defined BJT-MOSFET based Sziklai pair amplifier whereas Circuit-2 designates the similar amplifier design with Cadence system defined transistors at GPDK 180nm technology [17]-[18].

Table 3: Qualitative features of Proposed Amplifiers

Fig.2. Distribution of Voltage gain on Frequency Scale

Refer Table-3. Circuit-1(with PSpice user-defined BJT and MOSFET) carries significantly improved voltage and current gains, wider bandwidth, wider unity gain bandwidth, higher power consumption, and higher device voltage and current gain than Reference Amplifier on the cost of enhanced THD [18]. However, Circuit-2 (at GPDK 180nm technology) generates wider bandwidth, wider unity gain bandwidth, lower power consumption, and lower THD, than Reference Amplifier with the compromise over voltage and current gains. In spite of this, phase difference of the Circuit-1 and Circuit-2 is found lower than the Reference Amplifier. Moreover, due to typical CE-CD configuration, nearly 180^O phase reversal output is observed for all the amplifier circuits under consideration [19].

Fig.2 represents the voltage gain of all the amplifiers with respect to frequency. It is evident from Fig.2 that the Proposed amplifiers (Circuit-1 and Circuit-2) removes the narrow bandwidth restrictions of the Reference Amplifier and PNP driven Sziklai pair amplifier [7], [12]. Theses amplifiers are also found free from the poor-response-problem of small-signal Darlington pair amplifier at higher frequencies. Performance parameters observed in Table-3 suggests that proposed amplifiers may be used to design Cascadable gain blocks for radio and TV receiver stages and 1KHz-14MHz frequency range power sources [15], [20].

It must be mentioned that the performance of Circuit-1 strongly depends on Ideal maximum forward beta ‘β’ of user-defined BJT and Transconductance ‘V_TO’ of user-defined MOSFETs in PSpice [14]. It is found that voltage gain increases with increasing value of β and becomes saturated at higher β value whereas it decreases with increasing value of V_TO. In addition, meaningful amplification with β is received for 4 ≤ β ≤ 500 whereas for V_TO, the range for faithful amplification is -12 ≤ V_TO ≤ +3. The voltage gain of Circuit-1 increases with rising β because increasing β of the NPN transistors beyond β=4, causes increment in Small Signal transconductance, g_m and collector current I_C which perhaps increases the voltage gain of Circuit-1. In contrast, voltage gain of Circuit-1 decreases with increasing V_TO because small signal transconductance g_m decreases when the value of V_TO is varied beyond -12 to +3 range.

Proposed amplifiers may be used as Low Noise amplifier (LNA) in RF noise measurement system, shown in Fig.3 [21]. In this set-up, a biconical antenna is fed to bandpass filter through coaxial wires. The output of this filter is, then, applied to the LNA (having gain  30dB-60 dB in radio frequency region). The recording of the noise phase and quadrature data is performed with the help of spectrum analyser.

Fig.3. Block Diagram of Portable Noise Measurement System

B.    Small Signal AC Analysis

Small-signal AC equivalent circuit of Proposed amplifiers is depicted in Fig.4(a). With R_X=r_o||R_A and R_Y=r_d||R_S and R_B=R₁||R₂, the reduced version of Fig.4(a) is sketched in Fig.4(b).

Fig.4(a). Small-signal AC Equivalent of the Proposed amplifier

Fig.4(b). Small-signal AC Equivalent of the Proposed amplifier

Based on simulation results of Circuit-1, BJT of the Sziklai unit consists base-emitter resistance r_π=3.69KΩ, collector-emitter resistance r_o=1x10¹²Ω, AC current gain factor β=300 whereas MOSFET consists g_m=87.7x10^-3, drain-source resistance r_d=4.19KΩ [15].

Analysis of Fig.4(b) suggests that

Now voltage across register R_X would be

Hence,

Now, the voltage at input half

                  (3)

Now by Equation (2) and Equation (4)

Now, by Equation-5, small-signal AC voltage gain of the proposed amplifier may be expressed as-

Now by Equation (6)

Small-signal AC current gain of the proposed amplifier may be defined as-

C.    Performance Without R_A

Performance of the proposed circuits significantly depends on R_A which is to be necessarily included in circuit structure to retain amplification status [3], [16]. Table-4 summerizes the status of the parameters of the proposed circuits without R_A.

Table 4: Qualitative features of Proposed Amplifiers without R_A

Refer Table-4. Exclusion of R_A causes reduction in voltage and current gains of the proposed circuits (both A_VG and A_IG goes below unity). However, power consumption of both the proposed circuit reduces in the absence of R_A. In addition, THD of Circuit-1 remains constant whereas for Circuit-2, THD significantly reduces in the absence of R_A. This happens because of the fact that when R_A is detached from the Circuit-1, drain current I_D and drain-to-source voltage V_DS of P-type MOSFET decreases which consequently decreases the voltage and current gain across R_L.

  Fig.5. Effect of R_A on Voltage Gain

Fig.5 portrays the status of voltage gain of the proposed circuits as a function of R_A. Permissible range of R_A for Reference amplifier for meaningful amplification is 470Ω<R_A<5KΩ [7]. For Circuit-1 and Circuit-2, Voltage gain increases with increasing value of R_A up to R_A=5KΩ, and starts decreasing thereafter. It is also to note that both the proposed circuits produce distortion at R_A ≥15KΩ. Hence, the purposeful range for amplification of Circuit-1, and Circuit-2 is 1KΩ<R_A<15KΩ and 100Ω<R_A<15KΩ respectively. Observed phenomenon is found in accordance with the deduced Equations (6) and (7).

D.    Effect of Baising Resistances

Fig.6. shows the variation of the voltage gain of the proposed circuits with respect to Souce resistance R_S [9].

        Fig.6. Effect of R_S on Voltage Gain

The Voltage gain of Circuit-1 elevates with rising value of R_S and reaches its peak value at R_S= 15KΩ, and acquire decreasing trend at higher value of R_S. Similarly, in case of Circuit-2, voltage gain goes on increasing with increasing value of R_S.  However, this circuit produces distortion at R_S≥25KΩ. Therefore, meaningful range of amplification for Circuit-1 and Circuit-2 is 100Ω≤R_S≤100KΩ and 100Ω≤R_S≤25KΩ respectively. For Reference Amplifier, A_VG increases non-linearly with source resistance R_S and reaches its maximum value at R_S=12KΩ. Thus, purposeful response is received in 1KΩ<R_S<12KΩ range [7].  This generally happens because V_DS of P-type MOSFETs increases with increase in R_S (Upto 15KΩ) which in-turns increases the voltage gain of Circuit-1. However, beyond R_S≥15KΩ, drain to source voltage starts to reduce which reduces the voltage gain.

Fig.7. Effect of R_D on Voltage Gain

Fig.7 shows the variation of the maximum voltage gain with respect to drain resistance [12]. For Circuit-1, voltage gain rises with rising value of R_D and reaches to its peak value at R_D=2KΩ, thereafter starts decreasing non-linearly. It is also to note that this circuit produces distortions at R_D≥10KΩ. Hence, meaningful range for amplification with R_D for Circuit-1 is 100Ω<R_D<10KΩ. Similarly, voltage gain for Circuit-2 increases non-linearly with increasing value of R_D and attains its maximum value at R_D=2KΩ, and starts decreasing beyond this value. Therefore, meaningful range of R_D for Circuit-2 is 1KΩ≤R_D≤40KΩ.  However, for Reference Amplifier, voltage gain decreases with increasing values of drain resistance R_D up to 7KΩ and beyond this, amplifier performance becomes poor [7]. This usually happens because beyond 2KΩ, drain current and drain to source voltage both starts to decrease which is probably responsible for the deterioration of voltage gain.

It is also worth mentioning that the current gain of both the proposed amplifier circuits remain more or less unaffected with the variation of R_SS (Figure not shown) [19]. Instead, it is found that the voltage gain increases with decreasing value of R_SS for both the proposed circuits. However, for the Reference Amplifier, the voltage gain A_VG receives its maximum value at R_SS=10Ω and minimum value at R_SS=80KΩ [7].

E.    Effect of DC Supply Voltage 

Supply voltage scaling causes significant impact on the proposed amplifiers’ performance [13]. Fig.8 depicts the variation of voltage gain of the proposed circuits with respect to Supply Voltage V_DC. Respective observations are recorded up to V_DC=50V and beyond this limiting value, the proposed amplifiers appear with distorted outcome.

          Fig.8. Effect of V_DC on Voltage Gain

Fruitful range for amplification for Circuit-1 and Circuit-2 are observed to be 25 Volt ≥V_DC ≥ 5 Volt and 35 Volt ≥V_DC ≥10 Volt respectively. In addition, voltage gain for both the proposed amplifiers increases with increasing V_DC. However, Reference Amplifiers produces meaningful amplification with V_DC in the 7-40V range [7].  

The factor which is responsible for this behavior is the significant enhancement in drain to source voltage of the of P-type MOSFET at increasing values of V_DC which in-turns increases the effective voltage gain of the amplifiers.

F.     Phase Variation 

Phase difference of output voltage with respect to frequency is shown in Fig.9 for the proposed amplifier circuits [18], [22].

Fig.9. Phase Variation

At 1KHz of operating frequency, Circuit-2 produces higher phase reversal output (-123.624^O) than Circuit-1 (-112.173^O). However, Reference Amplifier generates phase reversal output close to 180^O (i.e. -163.479^O) [7]. With the increasing value of frequency, output phase difference of Circuit-2 initially decreases up to 100 Hz and undergoes sudden increment at 1KHz frequency, and thereafter increases non-linearly. Similarly, for Circuit-1, output phase difference changes in zig-zag manner up to 1KHz frequency, and increases non-linearly beyond this frequency.

G.   Temperature Dependent Performance

Table-5(a) and Table-5(b) refers the performance of the Circuit-1 and Circuit-2 with the variation of temperature in -20^OC ≤ T ≤ +50^OC range [23].

 Table-5(a): Temperature effect on Circuit-1 with PSpice User defined Transistors

Table-5(b): Temperature effect on Circuit-2 with Transistors Available at GPDK 180nm Technology

 Refer Table-5(a) and Table-5(b). Voltage and Current gain reduce whereas total power consumption increases for both the proposed amplifier circuits with rising temperature. However, bandwidth decreases with increasing temperature for Circuit-1, whereas for Circuit-2, it increases with temperature elevation. In addition, for reference amplifier, voltage gain goes down but current gain goes high with rising temperature [7]. This usually happens because the temperature elevation accelerates majority carrier generation process in both the proposed circuits which elevates collector and drain currents and therefore affects A_VG, A_IG and B_W [24].

This probably happens because the Drain-Source resistance of the P-type MOSFET rises with temperature which in turn reduces the drain current and the voltage and current gains [14]. Similarly, the bandwidth of proposed amplifiers also reduces with raising temperature for Circuit-1 because the effective drain to source capacitance of P-type MOSFET decreases with increasing temperature and causes reduction in the bandwidth [14].

H.   Noise Sensitivity

Variation of input and output noise with temperature (at different operational frequencies) for Circuit-1 and Circuit-2 is listed in  Table-6(a) and Table-6(b) respectively [24]-[25].

Table 6(a): Noise Sensitivity of Circuit-1 with PSpice User defined Transistors

Table 6(b): Noise Sensitivity of Circuit-2 with Transistors Available at GPDK 180nm Technology

Refer Table-6(a) and Table-6(b). Input noise of Circuit-1 and Circuit-2 at all the mentioned frequencies increases with increasing temperature. However, output noise of Circuit-1 at 10Hz, and 1KHz frequencies increases with increasing temperature whereas at 100KHz and 100MHz frequencies, it reduces with temperature elevation. Similarly, for Circuit-2, output noise at 10Hz, 1KHz, and 100MHz increases whereas at 100KHz, it decreases with rising temperature.

I.      Layout and Post layout Simulation

Fig.10. Layout of Circuit-2

J.     Monte Carlo Analysis

For 51 samples, Monte Carlo simulation is done to check the robustness of the proposed amplifiers for Voltage gain, and total power consumption against process and mismatch [29]. Statistical representation of such variations are shown in Fig.11, and Fig.12 respectively.

                                              Fig.11. Monte Carlo Simulation of Voltage gain

Fig.12. Monte Carlo Simulation of Total Power Consumption

K.   Process Corner Simulation

Fig. 13, and Fig.14 represents the five-corner simulation (TT, FF, SS, FNSP, SNFP) of voltage gain and total power consumption at 27^oC, where TT, FF, SS, FNSP, and SNFP stands for typical-typical, fast-fast, slow-slow, fast-NPN-slow-PMOS, and slow-NPN-fast-PMOS [30].

Fig.13. Corner Analysis of Voltage gain

Fig.14. Corner Analysis of Total Power Consumption

The SS corner simulation produces the largest Voltage gain, measuring 195.21 whereas the SS consumes lowest power consumption, measuring 47.1mW. In addition, all the corners have almost similar values of parameters at different corners which shows that the Circuit-2 is insensitive against the process and mismatch variations.

L.    Tuning Performance of Circuit-1

The Load capacitor C_L is included in Circuit-1 as an essential circuit component which help the amplifier to tune at a specific frequency to match the frequency of a particular channel [30]. It is achieved under two conditions, first by keeping the C_L constant at 1nF and varying C_D (Table-9(a)), and second by varying C_L and keeping C_D constant at 10μF (Table-9(b)).

Table-9(a): Performance parameters at Varying C_D and keeping C_L constant

 Table-9(b): Performance parameters at Varying C_L and keeping C_D constant

Refer Table-9(a) and Table-9(b). Tuning with C_D is achieved in 10μF-100mF range, while the range of tuning with C_L is 1nF-10nF. Fig. 15 shows two combinations of C_L and C_D which tune at a specific frequency with varying bandwidth.

Fig.15. Tuning Performance of Circuit-1

For Reference Amplifier, bandwidth varies with drain capacitor C_D and load capacitor C_L in 10μF–100μF and 0.001μF–.001F variation range respectively. However, in Circuit-2, C_L is not connected to the circuit structure hence no such type of tuning effect is recorded [9], [14].

M. Performance Summary and Comparison

Table-10 compiles the comparison of proposed amplifiers, Circuit-1 and Circuit-2, with the BJT-MOSFET hybrid unit based small signal Darlington pair amplifier and small signal amplifier with BJT-MOSFET hybrid unit under Sziklai pair topology [7], [11].

Table 10: Performance Summary and Comparison

Refer Table-10. Proposed Circuit-1 generates higher current and voltage gains, higher power gain, and lower THD than the amplifiers of Shukla et. al. [7] and Pratima et. al., [11]. However, Proposed Circuit-2 holds wide bandwidth, and higher power gain than [7], lower input noise than [11], lower THD than [7], lower power consumption than [7], [11].

In addition, Circuit-2 emerges with lowest power consumption, and lowest THD whereas Circuit-1 carries highest voltage and current gain, lowest Input referred noise, and higher power gain.

Conclusion

Two Circuit designs of small signal Sziklai pair amplifier with BJT-MOSFET hybrid unit are studied and analysed under the purview of present manuscript.

The proposed circuits commonly use CE-CD configuration; therefore, the entire unit produces 180^O phase shift in the output. In spite of this, proposed circuits provide solution to the poor frequency response of Darlington pairs at higher frequencies and narrow bandwidth limitations of small-signal PNP Sziklai pair amplifier. Additionally, these circuits also remove the narrow band problem of Reference Amplifier with comparatively high voltage and current gain as well as wider bandwidth.

The value of the additional biasing resistance R_A, as an essential circuit component, must be taken in the range 1KΩ<R_A<15KΩ and 100Ω<R_A<15KΩ for Circuit-1 and Circuit-2 respectively. In addition, for Circuit-1, meaningful amplification with ideal maximum forward beta β is received for the range 4 ≤ β ≤ 500 whereas for transconductance V_TO, the range for faithful amplification is -12 ≤ V_TO ≤ +3. It is also to be noted that load capacitor C_L acts as an essential circuit element for Circuit-1 to provide tuning whereas Circuit-2 does not require any load capacitor. Tuning performance of Circuit-1 can be availed with C_L=1nF, C_D=1μF and C_L=10nF, C_D=10μF. Comparison of proposed circuits with the similar small signal amplifiers design reported recently suggests voltage gains, current gains, input referred noise, bandwidth, THD, power consumption, and power gain as their prominent features.

Analysis of the proposed circuit suggests its use as Low Noise Amplifier in Street-scale Mapping of Radio frequency Noise at VHF and UHF region.

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